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Silaero
FPGA, ASIC, and Structured ASIC Technology
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For further details, please scroll down and click below on the technology of interest. For copies of issued US Patents, published applications, and PTO prosecution activity, please go to our page entitled "View IP at PTO".
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Hybrid-FPGA
What is a Hybrid-FPGA, anyway?
Ø An Application-Specific FPGA?
Ø A DSP Accelerator or co-processor?
Ø The first practical Embedded FPGA for Structured ASIC and SOC?
Well actually, it’s all three. In technical terms, it’s an FPGA with a Hybrid Interconnect Structure. In other words, a Hybrid FPGA fabric consists of a combination of logic modules and a unique combination of interconnect. The logic modules may have either fixed function or field-programmable function, while the interconnect between the modules consists of a (hybrid) combination of fixed wiring and field-programmable wiring.
One US Patent has issued and a Divisional Application has been filed.
To view more detailed information, please choose from one of the following topics:
Hybrid FPGA Architecture
Hybrid FPGA as a DSP Coprocessor
Hybrid FPGA as part of a Programmable Instruction DSP
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Structured SIP - Shippable ASIC Emulator
A Structured SIP (System-In-Package) performs the function of the final embedded processor-based ASIC with the identical footprint. It consists of a family of custom package substrates, each including a Processor ASIC device which contains many common functions. It also has provision to mount a standard packaged FPGA or Structured ASIC device on top.
It’s an emulator you can ship!
To view a detailed description, please click here.
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Binning for Structured ASICs
The First practical binning for solution for ASICs
Speed-grading (binning for speed) has been offered on standard semiconductor ICs for decades. Even FPGAs which are field-customizable are offered at different performance levels, often providing up to a 35% increase in speed and selling at up to a 100% premium. But FPGAs are actually manufactured as standard components. Speed grading, however, has never been offered for mask-programmed ASICs. Structured ASICs (module-based ASICs configured with a small number of custom masks) are now becoming more popular every day due to high mask costs for SOC Standard Cell Devices. For Structured ASICs as well as traditional mask-programmed gate arrays, an opportunity now exists to offer speed grading for ASICs - for the first time.
To view a detailed description, please click here.
This application was never published by the PTO.
To view the text as filed, please click here.
To view the drawings as filed, please click here.
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